Microcomputer having instruction RAM

ABSTRACT

A microcomputer comprises an instruction RAM temporally storing a program transferred from an external memory, a CPU reading out the program from the instruction RAM via a dedicated fetch bus and carrying out a process according to the program, an instruction transfer control circuit directly transferring the program from the external memory to the instruction RAM via a dedicated transfer bus, and a transfer information register temporally storing instruction transfer information which has been stored in the external memory and is necessary information for transferring the program from the external memory to the instruction RAM by the instruction transfer control circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to microcomputers, in particular, themicrocomputer incorporating an instruction RAM for temporarily storing aprogram to be executed in CPU.

2. Description of Related Art

In recent microcomputers, the processing speed of the incorporated CPUhas been increased, resulting in that the memory access delay causes thelimited CPU processing speed. In conventional configurations, in orderto reduce the memory weight of the CPU and shorten the processing time,a program is transferred from an external non-volatile memory to a fastinternal RAM and the program is then read out from the internal RAM.FIG. 5 shows an example of the conventional microcomputer which includesa RAM for temporarily storing such a program (hereafter, referred to as“instruction RAM”). The microcomputer with the configuration as shown inFIG. 5 is disclosed in, for example, Japanese Unexamined PatentApplication Publication No.2001-195261.

FIG. 5 shows a block diagram of the conventional microcomputer.

As shown in FIG. 5, the conventional microcomputer 3 comprises a CPU 31,an instruction RAM 32 which temporarily stores a program to be executedby the CPU 31, a memory control circuit (MEMC) 33 which reads out theprogram from an external memory 4 according to the instruction of theCPU 31 and transfers it to the instruction RAM 32, and a boot ROM 34which stores a boot program for controlling the program transfer fromthe external memory 4 to the instruction RAM 32 and a reset vector thatis the information determining the operation during the reset of theCPU. The CPU 31 is connected to the boot ROM 34 and the instruction RAM32 via dedicated buses (fetch bus) for reading out the programrespectively. The CPU 31 is connected to the memory control circuit 33via a system bus. The system bus and the fetch bus comprise the addressbus for transferring address signals (Add), and the data bus fortransferring programs (Ins) and data (Data).

In such a configuration, once the microcomputer in FIG. 5 starts up, theCPU 31 reads out the reset vector and the boot program from the boot ROM34 respectively, and first, carries out the known reset processaccording to the reset vector. Upon the completion of the reset process,the CPU 31 transfers the program from the external memory 4 to theinstruction RAM 32 via the system bus according to the boot program.Then, upon the completion of the program transfer based on the capacityof the instruction RAM 32 and the size of the program, the CPU 31 readsout the program transferred to the instruction RAM 32 via the fetch bus,and carries out the initial setting and the predetermined processaccording to the program in sequence.

As described above, in the conventional microcomputer, the programtransfer from the external memory to the internal instruction RAM iscontrolled at the CPU, so that other processes cannot be performed atthe CPU during the program transfer to the instruction RAM. Accordingly,the delay of the process occurs because it is required to wait until theprogram transfer to the instruction RAM is completed, causing theproblem of performance degradation of the microcomputer.

In addition, the program is transferred from the external memory to theinstruction RAM according to the boot program stored in the boot ROMthat is a non-volatile memory. Thus, there is a problem that it is noteasy to modify the weight information and the operation mode accordingto the type of the external memory, which is the transfer origination,and the transfer destination and transfer capacity of the program.

In addition, the read-instruction/write-instruction are repeatedlyissued from the CPU to the memory control circuit via the system bus toread out the program from the designated address of the external memoryand write the read program to the designated address of the instructionRAM, causing the problem of the slow program transfer speed.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided amicrocomputer comprising an instruction RAM temporally storing a programtransferred from an external memory, a CPU reading out the program fromthe instruction RAM via a dedicated fetch bus and carrying out a processaccording to the program, an instruction transfer control circuitdirectly transferring the program from the external memory to theinstruction RAM via a dedicated transfer bus, and a transfer informationregister temporally storing instruction transfer information which hasbeen stored in the external memory and is necessary information fortransferring the program from the external memory to the instruction RAMby the instruction transfer control circuit. In the microcomputerconfigured as above, the transfer of the program from the externalmemory to the instruction RAM is executed by the instruction transfercontrol circuit. Therefore, the CPU can carry out another process duringthe transfer of the program. Thus, the performance degradation of themicrocomputer due to the program transfer to the instruction RAM isprevented.

Further, the instruction transfer information necessary for the programtransfer is transferred from the external memory to the transferinformation register, and the program transfer from the external memoryto the instruction RAM is controlled by referring to the instructiontransfer information. Thus, the program transfer process can beoptimized according to the type of the external memory and the size ofthe program. In addition, the program is directly transferred from theexternal memory to the instruction RAM via the dedicated transfer bus bythe instruction transfer control circuit, allowing the program transferspeed to be improved.

According to another aspect of the present invention, there is provideda microcomputer comprising an instruction RAM temporally storing aprogram transferred from an external memory, an instruction transfercontrol circuit directly transferring the program from the externalmemory to the instruction RAM via a dedicated transfer bus, andgenerating a transfer completion signal indicative of the transfercompletion of the corresponding program every time when each transfer ofthe program to the instruction RAM is completed, a transfer informationregister temporally storing instruction transfer information which hasbeen stored in the external memory and is necessary information fortransferring the program from the external memory to the instruction RAMby the instruction transfer control circuit, and a monitor circuitmonitoring the transfer completion signal and a program read out fromthe instruction RAM by the CPU, and if the program read out by the CPUis not completed, sending a wait signal for keeping the readout of theprogram on standby to the CPU. The configuration of this inventioncomprises a monitor circuit which monitors a plurality of theinstruction RAMs, the transfer completion signal and the program read bythe instruction RAM. Thus, even if the program may include the branchstatement (the statement of jump or the like), it is possible, with asimple configuration, to keep the fetch of the program on standby at theCPU before the branched program is transferred to the instruction RAM.In particular, the configuration comprising a number of the instructionRAMs, each of which has relatively less capacity, allows the reducedwait time of the CPU.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing the first embodiment of themicrocomputer of the present invention;

FIG. 2 illustrates the memory map of the external memory andmicrocomputer shown in FIG. 1;

FIG. 3 is a block diagram showing the second embodiment of themicrocomputer of the present invention;

FIG. 4 illustrates the memory map of the external memory andmicrocomputer shown in FIG. 3;

FIG. 5 is a block diagram showing the conventional microcomputer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposed.

First Embodiment

FIG. 1 is a block diagram showing the first embodiment of themicrocomputer of the present invention, and FIG. 2 illustrates thememory map of the external memory and microcomputer shown in FIG. 1.

As shown in FIG. 1, the microcomputer 1 of the first embodiment has theconfiguration that comprises a CPU 11, an instruction RAM 12 whichtemporally stores the program executed in the CPU 11, an initial settingRAM 16 which temporally stores the reset vector and the program forinitial setting (initial setting program), an instruction transfercontrol circuit 14 which controls the program transfer from the externalmemory 2 to the instruction RAM 12 and the initial setting RAM 16, atransfer information register 15 which temporally stores the instructiontransfer information necessary for the program transfer from theexternal memory 2, and a memory control circuit (MEMC) 13 which controlsthe readout/write of the program and data to the external memory 2according to the instruction from the CPU 11. The instruction transfercontrol circuit 14 is connected to the instruction RAM 12 and theinitial setting RAM 16 via respective dedicated buses (transfer bus) fortransferring the program. The CPU 11 is connected to the instruction RAM12 and the initial setting RAM 16 via respective dedicated buses (fetchbus) for reading out the program. The CPU 11 and the memory controlcircuit 13 are connected via the system bus.

The system bus, the transfer bus and the fetch bus respectively comprisethe address bus for transferring the address signal and the data bus fortransferring the program (Ins) or data (Data). The instruction transferinformation stored in the transfer information register 15 includes thetype of the external memory 2 for reading out the program, thedestination address of the program, the number of transfers, the weightsetting and the operation mode of the external memory 2, and so on.

It should be noted that it is possible to connect the system bus to theDMA controller (DMAC) 17 which controls the transfer of the DirectMemory Access (DMA) of the program and data to the internal memory (notshown), and it may also be connected to the cash memory 18 whichtemporally stores the read out program and data from the external memory2 via the memory control circuit 13. In the configuration with the cashmemory 18, the CPU 11 can transfer the program and data from anyexternal memory 2 out of a plurality of the external memories 2connected to the memory control circuit 13, and carry out the process byreading out the program and data from the cash memory 18. In this case,upon the occurrence of the program fetch to the cash memory 18, the CPU11 may once stop the operation of the instruction transfer controlcircuit 14 and repeatedly issue the read-instruction/write-instructionto the memory control circuit 13. In this case, the CPU 11 can read outthe program from the designated address of the external memory 2 andwrite the read out program to the designated address of the cash memory18.

In such a configuration, according to the microcomputer 1 of the presentembodiment, the program transfer from the external memory 2 to theinstruction RAM 12 or the initial setting RAM 16 is controlled by theinstruction transfer control circuit 14.

When starting up or turning on the microcomputer, the instructiontransfer control circuit 14 first reads out the reset vector, the aboveinstruction transfer information and the initial setting program fromthe external memory 2 respectively, then writes the reset vector and theinitial setting program to the initial setting RAM 16, and writes theinstruction transfer information to the transfer information register 15by referring to FIG. 2. Next, the instruction transfer control circuit14 reads out the program (the program 0 in FIG. 2) from the externalmemory 2 in sequence, then transfers the read out program to theinstruction RAM 12 by referring to the instruction transfer informationstored in the transfer information register 15, and stores it in theaddress designated by the instruction transfer information. The programis directly transferred from the instruction transfer control circuit 14to the initial setting RAM 16 and the instruction RAM 12 via thetransfer bus as the way of the known DMA.

Upon the completion of the transfer of the reset vector and the initialsetting program to the initial setting RAM 16, the CPU 11 reads out thereset vector and the initial setting program from the initial settingRAM 16, and then carries out the predetermined reset process and initialsetting process according to the program.

During the reset process and the initial process by the CPU 11, theinstruction transfer control circuit 14 also reads out the program fromthe external memory 2 in sequence and transfers it to the instructionRAM 12. Upon the completion of the initial setting process, the CPU 11reads out the program which has so far been transferred to theinstruction RAM 12 in sequence, and carries out the predeterminedprocess according to the program.

Thus, according to the configuration of the present embodiment, it ispossible to transfer the program from the external memory 2 to theinstruction RAM 12 by the instruction transfer control circuit 14 and,at the same time, carry out the process by the CPU 11, preventing theperformance degradation of the microcomputer 1 due to the programtransfer process to the instruction RAM 12.

In addition, the external memory 2 stores the information including thedestination address, the number of the program transfers, the weightsetting and the operation mode of the external memory 2. When startingup the microcomputer 1, these pieces of the information are transferredto the transfer information register 15 from the external memory 2, andthe program transfer from the external memory 2 to the instruction RAM12 is controlled by referring to the information. Thus, the programtransfer process can be optimized according to the type of the externalmemory 2 and the size of the program. Further, the program is directlytransferred by the instruction transfer control circuit 14 via thededicated transfer bus from the external memory 2 to the instruction RAM12, so that the program transfer speed is improved.

Second Embodiment

The microcomputer 1 of the first embodiment reads out the program fromthe instruction RAM 12 at the CPU 11 and starts the process of theprogram before the completion of the transfer of the predetermined sizeof the program from the external memory 2 to the instruction RAM 12.Thus, if the branch statement (statement of jump or the like) isincluded in the program, the CPU 11 is required to keep the process onstandby until the transfer of the branched program to the instructionRAM 12 is completed by the instruction transfer control circuit 14 (waitprocess). The microprocessor 1 of the second embodiment provides theconfiguration for realizing a simple wait process.

FIG. 3 is a block diagram showing the second embodiment of themicrocomputer of the present invention, and FIG. 4 illustrates thememory map of the external memory and microcomputer shown in FIG. 3.

As shown in FIG. 3, the microcomputer of the second embodimentcomprises, in addition to the microcomputer 1 shown in the firstembodiment, a plurality of the instruction RAMs 0-n (n is a positiveinteger) and a monitor circuit 19 which monitors whether or not thetransfer of the program to each of the instruction RAMs 0-n iscompleted. Since other parts of the configuration are the same as thoseof the first embodiment, the explanation thereof is omitted. FIG. 3shows that the codes 120-12 n are assigned to the instruction RAMs 0-n.

The monitor circuit 19 comprises, for example, a table representing therelation between the transfer range (address) and the transfercompletion signals of the programs corresponding to respectiveinstruction RAMs 0-n. The monitor circuit 19 compares the readoutaddress of the program to respective instruction RAMs 0-n, which isissued by the CPU 11, with the transfer completion signal, which istransmitted from the instruction transfer control circuit 14. If theread out address of the program exceeds the transfer range of theprogram, that is, if the program read out by the CPU has not been sentto any of the instruction RAMs 0-n, the wait instruction for keeping thereadout of the program on standby is sent to the CPU 11. Upon thereception of the wait instruction from the monitor circuit 19, the CPU11 stops the program fetch from the instruction RAMs 0-n until the waitinstruction is canceled. In addition, in the configuration of themicrocomputer in accordance with the present invention, if employing anumber of the instruction RAMs, each of which has relatively lesscapacity, it is possible to detect the range of the transferred programon a smaller size basis. This allows the reduced time duration from thetime when the program to be read out has been transferred, to the timewhen the transfer completion signal is outputted, so that the wait timeof the CPU 11 is reduced.

According to the configuration of the second embodiment, even if theprogram includes the branch statement (the statement of jump or thelike), it is possible to keep the fetch of the program on standby at theCPU 11 until the branched program is transferred to the instruction RAMs0-n. In particular, it is possible to reduce the wait time of the CPU 11by employing the configuration having a number of instruction RAMs ofrelatively less capacity.

It is apparent that the present invention is not limited to the aboveembodiment and it may be modified and changed without departing from thescope and spirit of the invention.

1. A microcomputer comprising; an instruction RAM temporally storing aprogram transferred from an external memory, a CPU reading out theprogram from the instruction RAM via a dedicated fetch bus and carryingout a process according to the program, an instruction transfer controlcircuit directly transferring the program from the external memory tothe instruction RAM via a dedicated transfer bus, and a transferinformation register temporally storing instruction transfer informationwhich has been stored in the external memory and is necessaryinformation for transferring the program from the external memory to theinstruction RAM by the instruction transfer control circuit.
 2. Themicrocomputer of claim 1, further comprising; an initial setting RAMtemporally storing a reset vector and an initial setting programtransferred from the external memory, wherein the instruction transfercontrol circuit directly transfers the reset vector and the initialsetting program from the external memory to the initial setting RAM viaa dedicated transfer bus, and wherein the transfer information registertemporally stores instruction transfer information which has been storedin the external memory and is necessary information for transferring thereset vector and the initial setting program from the external memory tothe initial setting RAM by the instruction transfer control circuit. 3.The microcomputer of claim 1, further comprising; a memory controlcircuit, connected to the CPU via a system bus, executing readout/writeof a program and data to the external memory by the control of the CPUand a cash memory, connected to the system bus, temporally storing aprogram and data read out from the external memory via the memorycontrol circuit and being necessary for the process to be carried out atthe CPU.
 4. The microcomputer of claim 1, further comprising; a memorycontrol circuit, connected to the CPU via a system bus, executingreadout/write of a program and data to the external memory by thecontrol of the CPU, and a DMA controller controlling DMA transfer of aprogram and data read out from the external memory via the memorycontrol circuit to an internal memory and being necessary for theprocess to be carried out at the CPU.
 5. A microcomputer comprising; aninstruction RAM temporally storing a program transferred from anexternal memory, an instruction transfer control circuit directlytransferring the program from the external memory to the instruction RAMvia a dedicated transfer bus, and generating a transfer completionsignal indicative of the transfer completion of the correspondingprogram every time when each transfer of the program to the instructionRAM is completed, a transfer information register temporally storinginstruction transfer information which has been stored in the externalmemory and is necessary information for transferring the program fromthe external memory to the instruction RAM by the instruction transfercontrol circuit, and a monitor circuit monitoring the transfercompletion signal and a program read out from the instruction RAM by theCPU, and if the program read out by the CPU is not completed, sending await signal for keeping the readout of the program on standby to theCPU.
 6. The microcomputer of claim 5, further comprising; an initialsetting RAM temporally storing a reset vector and an initial settingprogram transferred from the external memory, wherein the instructiontransfer control circuit directly transfers the reset vector and theinitial setting program from the external memory to the initial settingRAM via a dedicated transfer bus, and wherein the transfer informationregister temporally stores instruction transfer information which hasbeen stored in the external memory and is necessary information fortransferring the reset vector and the initial setting program from theexternal memory to the initial setting RAM by the instruction transfercontrol circuit.
 7. The microcomputer of claim 5, further comprising; amemory control circuit, connected to the CPU via a system bus, executingreadout/write of a program and data to the external memory by thecontrol of the CPU and a cash memory, connected to the system bus,temporally storing a program and data readout from the external memoryvia the memory control circuit and being necessary for the process to becarried out at the CPU.
 8. The microcomputer of claim 5, furthercomprising; a memory control circuit, connected to the CPU via a systembus, executing readout/write of a program and data to the externalmemory by the control of the CPU, and a DMA controller controlling DMAtransfer of a program and data read out from the external memory via thememory control circuit to an internal memory and being necessary for theprocess to be carried out at the CPU.